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008			121018t20142014ctua b 001 0 eng
010			_a 2012952056
020			_a9781133628484
020			_a1133628486
035			_a(OCoLC)ocn828076941
040			_aYDXCP _beng _cLearning Resource Center _erda _dCNCEN _dIXA _dOCLCF _dUPM _dOCLCQ _dN5L _dDLC
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050	0	0	_aTK7868.L6 _bR67 2014
082	0	4	_223 _a621.395/R74
084			_aCCS
085	0	4	_aCCS 621.395/R74 _223
100	1		_aRoth, Charles H. _94666
245	1	0	_aFundamentals of logic design / _cCharles H. Roth, Jr., University of Texas at Austin, Larry L. Kinney, University of Minnesota, Twin Cities.
250			_aSeventh edition, International edition.
264			_aStamford, CT : _bCengage Learning, _c©2014
300			_axxiii, 791 pages : _billustrations (some color) ; _c24 cm + _e1 CD-ROM (4 3/4 in.)
336			_atext
500			_aRevision of: Fundamentals of logic design / Charles H. Roth, Jr., University of Texas at Austin, Larry L. Kinney, University of Minnesota, Twin Cities. -- Sixth edition. -- [Stamford, CT] : Cengage Learning, [2010]. Accompanying CD-ROM contains LogicAid, SimUaid, DirectVHDL-PE, user's guides, and examples.
504			_aIncludes bibliographical references (page 785) and index.
505	0		_aMachine generated contents note: Unit 1 Introduction Number Systems and Conversion -- Objectives -- Study Guide -- 1.1. Digital Systems and Switching Circuits -- 1.2. Number Systems and Conversion -- 1.3. Binary Arithmetic -- 1.4. Representation of Negative Numbers -- Sign and Magnitude Numbers -- 2's Complement Numbers -- Addition of 2's Complement Numbers -- 1's Complement Numbers -- Addition of 1's Complement Numbers -- 1.5. Binary Codes -- Problems -- Unit 2 Boolean Algebra -- Objectives -- Study Guide -- 2.1. Introduction -- 2.2. Basic Operations -- 2.3. Boolean Expressions and Truth Tables -- 2.4. Basic Theorems -- 2.5.Commutative, Associative, Distributive, and DeMorgan's Laws -- 2.6. Simplification Theorems -- 2.7. Multiplying Out and Factoring -- 2.8.Complementing Boolean Expressions -- Problems -- Unit 3 Boolean Algebra (Continued) -- Objectives -- Study Guide -- 3.1. Multiplying Out and Factoring Expressions -- 3.2. Exclusive-OR and Equivalence Operations -- 3.3. The Consensus Theorem -- 3.4. Algebraic Simplification of Switching Expressions -- 3.5. Proving Validity of an Equation -- Programmed Exercises -- Problems -- Unit 4 Applications of Boolean Algebra Minterm and Maxterm Expansions -- Objectives -- Study Guide -- 4.1. Conversion of English Sentences to Boolean Equations -- 4.2.Combinational Logic Design Using a Truth Table -- 4.3. Minterm and Maxterm Expansions -- 4.4. General Minterm and Maxterm Expansions -- 4.5. Incompletely Specified Functions -- 4.6. Examples of Truth Table Construction -- 4.7. Design of Binary Adders and Subtracters -- Problems -- Unit 5 Karnaugh Maps -- Objectives -- Study Guide -- 5.1. Minimum Forms of Switching Functions -- 5.2. Two-and Three-Variable Karnaugh Maps -- 5.3. Four-Variable Karnaugh Maps -- 5.4. Determination of Minimum Expressions Using Essential Prime Implicants -- 5.5. Five-Variable Karnaugh Maps -- 5.6. Other Uses of Karnaugh Maps -- 5.7. Other Forms of Karnaugh Maps -- Programmed Exercises -- Problems -- Unit 6 Quine-McCluskey Method -- Objectives -- Study Guide -- 6.1. Determination of Prime Implicants -- 6.2. The Prime Implicant Chart -- 6.3. Petrick's Method -- 6.4. Simplification of Incompletely Specified Functions -- 6.5. Simplification Using Map-Entered Variables -- 6.6. Conclusion -- Programmed Exercise -- Problems -- Unit 7 Multi-Level Gate Circuits NAND and NOR Gates -- Objectives -- Study Guide -- 7.1. Multi-Level Gate Circuits -- 7.2. NAND and NOR Gates -- 7.3. Design of Two-Level NAND-and NOR-Gate Circuits -- 7.4. Design of Multi-Level NAND-and NOR-Gate Circuits -- 7.5. Circuit Conversion Using Alternative Gate Symbols -- 7.6. Design of Two-Level, Multiple-Output Circuits -- Determination of Essential Prime Implicants for Multiple-Output Realization -- 7.7. Multiple-Output NAND-and NOR-Gate Circuits -- Problems -- Unit 8 Combinational Circuit Design and Simulation Using Gates -- Objectives -- Study Guide -- 8.1. Review of Combinational Circuit Design -- 8.2. Design of Circuits with Limited Gate Fan-In -- 8.3. Gate Delays and Timing Diagrams -- 8.4. Hazards in Combinational Logic -- 8.5. Simulation and Testing of Logic Circuits -- Problems -- Design Problems -- Seven-Segment Indicator -- Unit 9 Multiplexers, Decoders, and Programmable Logic Devices -- Objectives -- Study Guide -- 9.1. Introduction -- 9.2. Multiplexers -- 9.3. Three-State Buffers -- 9.4. Decoders and Encoders -- 9.5. Read-Only Memories -- 9.6. Programmable Logic Devices -- Programmable Logic Arrays -- Programmable Array Logic -- 9.7.Complex Programmable Logic Devices -- 9.8. Field-Programmable Gate Arrays -- Decomposition of Switching Functions -- Problems -- Unit 10 Introduction to VHDL -- Objectives -- Study Guide -- 10.1. VHDL Description of Combinational Circuits -- 10.2. VHDL Models for Multiplexers -- 10.3. VHDL Modules -- Four-Bit Full Adder -- 10.4. Signals and Constants -- 10.5. Arrays -- 10.6. VHDL Operators -- 10.7. Packages and Libraries -- 10.8. IEEE Standard Logic -- 10.9.Compilation and Simulation of VHDL Code -- Problems -- Design Problems -- Unit 11 Latches and Flip-Flops -- Objectives -- Study Guide -- 11.1. Introduction -- 11.2. Set-Reset Latch -- 11.3. Gated Latches -- 11.4. Edge-Triggered D Flip-Flop -- 11.5.S-R Flip-Flop -- 11.6.J-K Flip-Flop -- 11.7.T Flip-Flop -- 11.8. Flip-Flops with Additional Inputs -- 11.9. Asynchronous Sequential Circuits -- 11.10. Summary -- Problems -- Programmed Exercise -- Unit 12 Registers and Counters -- Objectives -- Study Guide -- 12.1. Registers and Register Transfers -- Parallel Adder with Accumulator -- 12.2. Shift Registers -- 12.3. Design of Binary Counters -- 12.4. Counters for Other Sequences -- Counter Design Using D Flip-Flops -- 12.5. Counter Design Using S-R and J-K Flip-Flops -- 12.6. Derivation of Flip-Flop Input Equations -- Summary -- Problems -- Unit 13 Analysis of Clocked Sequential Circuits -- Objectives -- Study Guide -- 13.1.A Sequential Parity Checker -- 13.2. Analysis by Signal Tracing and Timing Charts -- 13.3. State Tables and Graphs -- Construction and Interpretation of Timing Charts -- 13.4. General Models for Sequential Circuits -- Programmed Exercise -- Problems -- Unit 14 Derivation of State Graphs and Tables -- Objectives -- Study Guide -- 14.1. Design of a Sequence Detector -- 14.2. More Complex Design Problems -- 14.3. Guidelines for Construction of State Graphs -- 14.4. Serial Data Code Conversion -- 14.5. Alphanumeric State Graph Notation -- 14.6. Incompletely Specified State Tables -- Programmed Exercises -- Problems -- Unit 15 Reduction of State Tables State Assignment -- Objectives -- Study Guide -- 15.1. Elimination of Redundant States -- 15.2. Equivalent States -- 15.3. Determination of State Equivalence Using an Implication Table -- 15.4. Equivalent Sequential Circuits -- 15.5. Reducing Incompletely Specified State Tables -- 15.6. Derivation of Flip-Flop Input Equations -- 15.7. Equivalent State Assignments -- 15.8. Guidelines for State Assignment -- 15.9. Using a One-Hot State Assignment -- Problems -- Unit 16 Sequential Circuit Design -- Objectives -- Study Guide -- 16.1. Summary of Design Procedure for Sequential Circuits -- 16.2. Design Example -- Code Converter -- 16.3. Design of Iterative Circuits -- Design of a Comparator -- 16.4. Design of Sequential Circuits Using ROMs and PLAs -- 16.5. Sequential Circuit Design Using CPLDs -- 16.6. Sequential Circuit Design Using FPGAs -- 16.7. Simulation and Testing of Sequential Circuits -- 16.8. Overview of Computer-Aided Design -- Design Problems -- Additional Problems -- Unit 17 VHDL for Sequential Logic -- Objectives -- Study Guide -- 17.1. Modeling Flip-Flops Using VHDL Processes -- 17.2. Modeling Registers and Counters Using VHDL Processes -- 17.3. Modeling Combinational Logic Using VHDL Processes -- 17.4. Modeling a Sequential Machine -- 17.5. Synthesis of VHDL Code -- 17.6. More About Processes and Sequential Statements -- Problems -- Simulation Problems -- Unit 18 Circuits for Arithmetic Operations -- Objectives -- Study Guide -- 18.1. Serial Adder with Accumulator -- 18.2. Design of a Binary Multiplier -- 18.3. Design of a Binary Divider -- Programmed Exercises -- Problems -- Unit 19 State Machine Design with SM Charts -- Objectives -- Study Guide -- 19.1. State Machine Charts -- 19.2. Derivation of SM Charts -- 19.3. Realization of SM Charts -- Problems -- Unit 20 VHDL for Digital System Design -- Objectives -- Study Guide -- 20.1. VHDL Code for a Serial Adder -- 20.2. VHDL Code for a Binary Multiplier -- 20.3. VHDL Code for a Binary Divider -- 20.4. VHDL Code for a Dice Game Simulator -- 20.5. Concluding Remarks -- Problems -- Lab Design Problems -- A. Appendices -- A. MOS and CMOS Logic -- B. VHDL Language Summary -- C. Tips for Writing Synthesizable VHDL Code -- D. Proofs of Theorems -- E. Answers to Selected Study Guide Questions and Problems.
520			_aUpdated for this 7th edition, this text achieves a balance between theory and application. It presents the theory that is necessary for understanding the fundamental concepts of logic design while not overwhelming students with the mathematics of switching theory.
521			_aCOECS
650		0	_aLogic circuits. _9806
650		0	_aLogic design. _91047
650		0	_aLogic design _vProblems, exercises, etc. _94667
650		7	_aLogic circuits. _2fast _9806
650		7	_aLogic design. _2fast _91047
655		7	_aProblems, exercises, etc. _2fast _94668
700	1		_aKinney, Larry L. _94669
856	4	2	_3Contributor biographical information _uhttp://www.loc.gov/catdir/enhancements/fy1516/2012952056-b.html
856	4	2	_3Publisher description _uhttp://www.loc.gov/catdir/enhancements/fy1516/2012952056-d.html
856	4	1	_3Table of contents only _uhttp://www.loc.gov/catdir/enhancements/fy1516/2012952056-t.html
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